1. Field of the Invention
The present invention relates to a semiconductor device and method of manufacturing the semiconductor device, especially to a semiconductor device and the associated manufacturing method that utilize a 3D (three-dimensional) structural semiconductor device to implement an ESD (electrostatic discharge) protection circuit, so as to reduce circuit areas.
2. Description of Related Art
ESD protection is significant in the semiconductor field. In particular, when the semiconductor manufacturing process is more compact and the line width becomes thinner, the integrated circuits are exposed to higher threats of all kinds of ESDs, such as HBM (Human-Body Model) ESD, MM (Machine Model) ESD, and CDM (Charged-Device Model) ESD. Please refer to FIG. 1, illustrating a conventional ESD protection circuit. The main circuit 150 inside an IC chip uses an input pad 130 and an output pad 140 to communicate with circuits outside the IC chip. The input pad 130 and the output pad 140 are connected respectively to an ESD protection circuit 110 and an ESD protection circuit 120. The ESD protection circuit 110 is composed of a PMOS 112 and an NMOS 114, which are connected in series, and the ESD protection circuit 120 is composed of a PMOS 122 and an NMOS 124, which are connected in series. This ESD protection circuit has a disadvantage that the PMOS/NMOS occupies too much area. Another ESD protection circuit composed of diodes has the same problem.